Dual display device

ABSTRACT

A dual display device includes a display panel having a first surface and an opposing second surface, and including a plurality of first pixels displaying an image on the first surface and a plurality of second pixels displaying an image on the second surface, a gate driver supplying gate signals to the first and second pixels, a signal controller including first and second receivers receiving input image signals and generating first and second output image signals based on the input image signals, and a data driver analog-converting the first and second output image signals to generate first and second data voltages, respectively, and supplying the first and second data voltages to the first and second pixels, respectively. By using two different interfaces, memories can be reduced by driving transmissive pixels and reflective pixels independently, and different normal images can be displayed on both surfaces of the display panel. When the same image is displayed on both surfaces, only one interface is selectively driven to thereby reduce power consumption.

This application claims priority to Korean Patent Application No.10-2006-0063355, filed on Jul. 6, 2006, and all the benefits accruingtherefrom under 35 U.S.C. § 119, the contents of which in its entiretyare herein incorporated by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a display device, and more particularlyto a dual display device.

(b) Description of the Related Art

Generally, a liquid crystal display device includes a pair of panelsprovided with pixel electrodes and a common electrode, and a liquidcrystal layer with dielectric anisotropy interposed between the panels.The liquid crystal display device controls the transmittance of lightpassing through the liquid crystal layer by applying an electric fieldto the liquid crystal layer and adjusting the field strength fordisplaying desired images.

Because the LCD device is a light-receiving device which is incapable ofself-emitting light, light emitted by lamps of a separately providedbacklight unit passes through the liquid crystal layer, or externallight, such as natural light, passes through the liquid crystal layertwice by reflection. The first described LCD device is called a“transmissive” type of LCD device and the latter described LCD device iscalled a “reflective” type of LCD device. The reflective type of LCDdevice is commonly used in medium and small display devices. Anothertype of LCD device is a “transflective” or “reflective-transmissive” LCDdevice which is capable of selectively using light from the backlightunit and external light in response to existing circumstances. Thetransflective LCD device is commonly used in medium and small displaydevices.

In the transflective LCD device, each pixel has a transparent electrodeand a reflective electrode electrically connected to each other. Thelight emitted from the backlight unit passes through the transparentelectrode for use in display and the external light entering from theopposite side of the backlight unit is reflected from the reflectiveelectrode for use in display. Therefore, images are always displayed ononly one surface of the liquid crystal panel assembly.

Accordingly, in this case, when the liquid crystal panel assembly isviewed from the other opposite side surface, an image whose left andright are reversed is seen.

When it is desired to display an image on both side surfaces in a mobilephone or the like, two liquid crystal panel assemblies overlap eachother so that only the outer surfaces of each of the two liquid crystalpanel assemblies are used for display. However, although an image can bedisplayed on both sides of the display device, the thickness of theoverall display device is larger.

BRIEF SUMMARY OF THE INVENTION

An aspect of the present invention provides a dual display device whichdisplays images with identical or different constant phases on both sidesurfaces, and reduces the capacitance of the device.

To overcome the above-described problems, according to one exemplaryembodiment of the present invention, a display device includes: adisplay panel having a first surface and a second surface facing eachother, and including a plurality of first pixels for displaying an imageon the first surface and a plurality of second pixels displaying animage on the second surface; a gate driver supplying gate signals to thefirst and second pixels; a signal controller including first and secondreceivers receiving input image signals, and generating first and secondoutput image signals based on the input image signals; and a data driverthat analog-converts the first and second output image signals togenerate first and second data voltages, respectively, and supplies thefirst and second data voltages to the first and second pixels,respectively.

The first pixels and the second pixels may be arranged in an alternatingfashion. The display panel may include data lines connected to the firstand second pixels, and the data driver may apply the first data voltageand the second data voltage to the data lines in an alternating fashion.

The first pixel may include a transmissive pixel electrode, and thesecond pixel may include a reflective pixel electrode.

The dual display device may further include a backlight unit irradiatinglight toward the display panel, wherein the transmissive pixel electrodemay transmit the light from the backlight unit toward the first surfaceof the display panel, and the reflective pixel electrode may reflect thelight from the backlight unit toward the second surface thereof.

The signal controller may further include a signal arrangement unitgenerating the first output image signal and the second output imagesignal based on the input image signals received from at least one ofthe first and second receivers, and outputting the first output imagesignal and the second output image signal to the data driver in analternating fashion.

The first receiver may include a first memory unit which stores theimage signals, and which may be controlled by an external controlsignal.

The input image signals may include a first input image signal to bedisplayed on the first surface and a second input image signal to bedisplayed on the second surface, the first receiver may receive thefirst input image signal to store the same in the first memory unit, thesecond receiver may receive the second input image signal to output thesame, and the signal arrangement unit may generate the first outputimage signal from the first input image signal and the second outputimage signal from the second input image signal.

The signal arrangement unit may include: a second memory unit receivingthe first input image signal from the first memory unit to store thesame therein; a third memory unit receiving the second input imagesignal from the second receiver to store the same therein, and a fourthmemory unit receiving the first input image signal and the second inputimage signal from the second memory unit and the third memory unit in analternating fashion to store the same therein.

An image of the first pixels and an image of the second pixels may bedifferent from each other.

An image viewed from the first surface of the display panel and an imageviewed from the second surface thereof may be identical to each other.

The signal controller may generate the first output image signal and thesecond output image signal based on the input image signals receivedfrom at least one of the first and second receivers.

In this case, the signal controller may further include a firstswitching unit selecting one of the first and second receivers andtransmitting the input image signals thereto.

The first switching unit may include: a first switch monitoring theconnection between the first receiver and the input image signals; and asecond switch monitoring the connection between the second receiver andthe input image signals and operating opposite to the first switch.Alternatively, the first switching unit may include a switch connectedto the input image signals and selectively connected to one of the firstand second receivers.

The signal arrangement unit may include a delay unit delaying the inputimage signals.

The signal arrangement unit may further include a second memory unitconnected to the first receiver and a third memory unit connected to thesecond receiver, and the signal arrangement unit may have an outputterminal.

The delay unit may receive the input image signals from one of thesecond and third memory units. Alternatively, the delay unit may receivethe input image signals from one of the first and second receivers andoutput the input image signals to one of the second and third memoryunits.

The signal arrangement unit may include a second switching unitmonitoring the connection among the second memory unit, the third memoryunit, the delay unit and the output terminal. The second switching unitmay include a first switch monitoring the connection between the secondmemory unit or the third memory unit and the output terminal, a secondswitch monitoring the connection between the second memory unit or thethird memory unit and the delay unit, and a third switch monitoring theconnection between the delay unit and the output terminal. At this time,a conduction time of the first switching unit and the second switchingunit may be different from a conduction time of the third switchingunit.

The signal arrangement unit may output the first output image signal andthe second output image signal in a reverse order.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more apparent by describing exemplaryembodiments thereof in more detail with reference to the accompanyingdrawings, in which:

FIG. 1 is a block diagram of a liquid crystal display device accordingto an exemplary embodiment of the present invention;

FIG. 2 is an equivalent circuit schematic diagram of one pixel in aliquid crystal display device according to an exemplary embodiment ofthe present invention;

FIG. 3 is a plan view layout of a liquid crystal panel assemblyaccording to an exemplary embodiment of the present invention;

FIG. 4 is a cross-sectional view of the liquid crystal panel assemblytaken along line IV-IV of FIG. 3;

FIG. 5 is a cross-sectional view of the liquid crystal panel assemblytaken along line V-V of FIG. 3;

FIG. 6 is a block diagram of a signal controller according to anexemplary embodiment of the present invention;

FIG. 7 is a block diagram of a signal controller according to anotherexemplary embodiment of the present invention; and

FIG. 8 is a block diagram of a signal controller according to stillanother exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the present invention are shown. This invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein. Rather, these embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art.Like reference numerals refer to like elements throughout.

It will be understood that when an element is referred to as being “on”another element, it can be directly on the other element or interveningelements may be present therebetween. In contrast, when an element isreferred to as being “directly on” another element, there are nointervening elements present. Further, it will be understood that when afirst element is referred to as being “on” a second element, the firstelement may be above or below the second element. As used herein, theterm “and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” or “includes” and/or “including” when used in thisspecification, specify the presence of stated features, regions,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,regions, integers, steps, operations, elements, components, and/orgroups thereof.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother elements as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in one of the figures is turned over, elementsdescribed as being on the “lower” side of other elements would then beoriented on “upper” sides of the other elements. The exemplary term“lower”, can therefore, encompasses both an orientation of “lower” and“upper,” depending of the particular orientation of the figure.Similarly, if the device in one of the figures is turned over, elementsdescribed as “below” or “beneath” other elements would then be oriented“above” the other elements. The exemplary terms “below” or “beneath”can, therefore, encompass both an orientation of above and below.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thepresent disclosure, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Exemplary embodiments of the present invention are described herein withreference to cross section illustrations that are schematicillustrations of idealized embodiments of the present invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the present invention should not beconstrued as limited to the particular shapes of regions illustratedherein but are to include deviations in shapes that result, for example,from manufacturing. For example, a region illustrated or described asflat may, typically, have rough and/or nonlinear features. Moreover,sharp angles that are illustrated may be rounded. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the precise shape of a region and are notintended to limit the scope of the present invention.

The present invention will be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the present invention are shown. As those skilled in the art wouldrealize, the described exemplary embodiments may be modified in variousdifferent ways, all without departing from the spirit or scope of thepresent invention.

FIG. 1 is a block diagram of a liquid crystal display device accordingto an exemplary embodiment of the present invention. FIG. 2 is anequivalent circuit schematic diagram of one pixel in a liquid crystaldisplay device according to an exemplary embodiment of the presentinvention.

As shown in FIG. 1, a liquid crystal display device according to anexemplary embodiment of the present invention includes a liquid crystalpanel assembly 300, a gate driver 400, a data driver 500, a gray voltagegenerator 800, a backlight unit 900 and a signal controller 600.

The liquid crystal panel assembly 300 includes a plurality of signallines G₁-G_(2n) and D₁-D_(m) and a plurality of first and second pixelsPXa and PXb connected thereto and arranged substantially in a matrixconfiguration. The liquid crystal panel assembly 300 shown in FIG. 2includes lower and upper panels 100 and 200 facing each other, and aliquid crystal layer 3 interposed therebetween.

The signal lines G₁-G_(2n) and D₁-D_(m) include a plurality of first andsecond gate lines G₁-G_(2n) transmitting gate signals (called scanningsignals), and a plurality of data lines D₁-D_(m) transmitting datasignals. The gate lines G₁-G_(2n), extend substantially in a rowdirection and are substantially parallel to each other, while the datalines D₁-D_(m) extend substantially in a column direction crossing thegate lines G₁-G_(2n) and are substantially parallel to each other.

The first pixel PXa and the second pixel PXb each display images onopposite surfaces of the liquid crystal panel assembly 300. Forinstance, if the first pixel PXa displays an image on the rear surfaceof the liquid crystal panel assembly 300, the second pixel PXb displaysan image on the front surface thereof, or vice versa.

Referring to FIG. 2, the first and second pixels PXa and PXb forming apair are connected to corresponding gate lines GLa and GLb,respectively, and are connected to one data line DL. Each pixel PXa/PXbincludes a switching element Qa/Qb connected to the signal lines GLa/GLband DL, a liquid crystal capacitor Clca/Clcb, and a storage capacitorCsta/Cstb.

The switching element Qa/Qb, such as a thin film transistor (“TFT”), forexample, is provided on the lower panel 100 and has three terminals: acontrol terminal connected to the gate line GLa/GLb; an input terminalconnected to the data line DL; and an output terminal connected to theliquid crystal capacitor Clca/Clcb and the storage capacitor Csta/Cstb.

The liquid crystal capacitor Clca/Clcb includes a pixel electrode 191a/191 b provided on the lower panel 100 and a common electrode 270provided on the upper panel 200 as two terminals. The liquid crystallayer 3 disposed between the two electrodes 191 a/191 b and the commonelectrode 270 functions as a dielectric material. The pixel electrode191 a/191 b is connected to the switching element Qa/Qb, and the commonelectrode 270 is supplied with a common voltage Vcom and covers theentire surface of the upper panel 200. Alternatively, the commonelectrode 270 may be provided on the lower panel 100, and at least oneof the two electrodes 191 a/191 b and the common electrode 270 may haveshapes of bars or stripes. The first pixel electrode 191 a may be atransparent transmissive electrode, and the second pixel electrode 191 bmay be a reflective electrode, or vice versa.

The storage capacitor Csta/Cstb is an auxiliary capacitor for the LCcapacitor Clca/Clcb. The storage capacitor Clca/Clcb includes the pixelelectrode 191 a/191 b and a separate signal line which is provided onthe lower panel 100. The storage capacitor Clca/Clcb overlaps the pixelelectrode 191 a/191 b via an insulator, and is supplied with apredetermined voltage such as the common voltage Vcom.

For color display, each pixel PXa and PXb uniquely represents one ofprimary colors (e.g., spatial division) or each pixel Pxa and PXbsequentially represents the primary colors in turn (e.g., temporaldivision) such that a spatial or temporal sum of the primary colors isrecognized as a desired color. An example of a set of the primary colorsincludes red, green and blue colors, for example, but is not limitedthereto. FIG. 2 shows an example of spatial division in which the pairof pixels PXa and PXb includes a color filter 230 representing one ofthe primary colors in an area of the upper panel 200 facing the pair ofpixel electrodes 191 a and 191 b. Alternatively, the color filter 230 isprovided on or under the pixel electrodes 191 a/191 b on the lower panel100.

At least one polarizer (not shown) is attached to an outer surface ofthe liquid crystal panel assembly 300.

A detailed structure of the liquid crystal panel assembly 300 accordingto an exemplary embodiment of the present invention will now bedescribed in more detail with reference to FIGS. 3 to 5.

FIG. 3 is a layout view of a liquid crystal panel assembly according toan exemplary embodiment of the present invention. FIG. 4 is across-sectional view of the liquid crystal panel assembly taken alongline IV-IV in FIG. 3. FIG. 5 is a cross-sectional view of the liquidcrystal panel assembly taken along line V-V in FIG. 3.

The liquid crystal panel assembly 300 according to the present exemplaryembodiment includes a thin film transistor array panel 100 and a commonelectrode panel 200 facing each other, and a liquid crystal layer 3interposed between the two panels 100 and 200.

First, the thin film transistor array panel 100 will be described inmore detail.

A plurality of first and second gate lines 121 a and 121 b and aplurality of storage electrode lines 131 are disposed on an insulatingsubstrate 110 made of transparent glass or the like.

The gate lines 121 a and 121 b substantially extend in a transversedirection and are arranged in an alternating fashion, as illustrated inFIG. 3. The first gate lines 121 a include a plurality of first gateelectrodes 124 a protruding downward and a plurality of end portions 129a having a wider area than the first gate lines 121 a for connection toother layers or external apparatuses (not shown). The second gate lines121 b include a plurality of second gate electrodes 124 b disposed underthe first gate lines 121 a and protruding upward and a plurality of endportions 129 b having a wider area than the second gate lines 121 b forconnection to other layers or external apparatuses (not shown). A gatedriving circuit (not shown) for generating gate signals may be mountedon a flexible printed circuit film (not shown), which may be attached tothe substrate 110, directly mounted on the substrate 110, or integratedonto the substrate 110. The gate lines 121 a and 121 b may extend to beconnected to a gate driving circuit which may be integrated on thesubstrate 110.

The storage electrode lines 131 are supplied with a predeterminedvoltage, and extend somewhat parallel to the gate lines 121 a and 121 b,as illustrated in FIG. 3. Each of the storage electrode lines 131 isdisposed between the first gate lines 121 a and the second gate lines121 b so as to be closer to the second gate lines 121 b disposed atlower sides. The storage electrode lines 131 include projections 137 and138 protruding upward, as illustrated in FIG. 3. The shapes andarrangement of the storage electrode lines 131 may be modified invarious manners.

The gate lines 121 a and 121 b and the storage electrode lines 131 maybe made of an aluminum-based metal such as aluminum (Al) or an aluminumalloy, a silver-based metal such as silver (Ag) or a silver alloy, acopper-based metal such as copper (Cu) or a copper alloy, amolybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy,chromium (Cr), titanium (Ti), or tantalum (Ta). However, the gate lines121 a and 121 b and the storage electrode lines 131 may have amulti-layered structure including two conductive layers (not shown)having different physical properties. One of the two conductive layersis made of a metal having low resistivity, for example, analuminum-based metal, a silver-based metal, or a copper-based metal, inorder to reduce signal delay or voltage drop. The other conductivelayers are made of a material having good contact characteristics toother materials, particularly to indium tin oxide (“ITO”) or indium zincoxide (“IZO”), such as a molybdenum-based metal, chromium, titanium, ortantalum. As preferred exemplary embodiments thereof, there are acombination of a lower chromium layer and an upper aluminum (alloy)layer and a combination of a lower aluminum (alloy) layer and an uppermolybdenum (alloy) layer. However, the gate lines 121 a and 121 b andthe storage electrode lines 131 may be made of various metals andconductive materials not explicitly listed herein.

The side surfaces of the gate lines 121 a and 121 b and the storageelectrode lines 131 are slanted with respect to a surface of thesubstrate 110 so as to form an angle in the range of about 30° to about80° with respect to the substrate 110.

A gate insulating film 140 made of a silicon nitride (“SiNx”), siliconoxide (“SiOx”), or the like, is formed on the gate lines 121 a and 121 band the storage electrode lines 131.

A plurality of first and second island-type semiconductors 154 a and 154b made of hydrogenated amorphous silicon (abbreviated to “a-Si”) orpolysilicon are formed above the gate insulating film 140. Thesemiconductors 154 a and 154 b are disposed on the gate electrodes 124 aand 124 b, respectively.

A plurality of pairs of first island-type ohmic contact members 163 aand 165 a are formed over the first semiconductors 154 a, and aplurality of pairs of second island-type ohmic contact members 163 b and165 b are formed over the second semiconductors 154 b. The ohmiccontacts 163 a, 163 b, 165 a and 165 b are made of silicide or an n+hydrogenated amorphous silicon or the like which is heavily doped withn-type impurities.

The side surfaces of the semiconductors 154 a and 154 b and the ohmiccontact members 163 a, 163 b, 165 a and 165 b are slanted with respectto the surface of the substrate 110 to form an angle in the range ofabout 30° to about 80° with respect to the substrate 110.

A plurality of data lines 171 and a plurality of first and second drainelectrodes 175 a and 175 b are formed on the ohmic contact members 163a, 163 b, 165 a and 165 b and the gate insulating film 140.

The data lines 171 substantially extend in a longitudinal direction tointersect the gate lines 121 a and 121 b and the storage electrode lines131, as illustrated in FIG. 3, and transmit the data signals. Each ofthe data lines 171 has a plurality of first and second source electrodes173 a and 173 b, respectively, which extend toward the gate electrodes124 a and 124 b, and end portions 179 which have enlarged widths forconnection to other layers or external apparatuses (not shown). A datadriving circuit (not shown) for generating data signals may be mountedon a flexible printed circuit film (not shown), which may be attached tothe substrate 110, directly mounted on the substrate 110, or integratedonto the substrate 110. The data lines 171 may extend to be connected toa data driving circuit which may be integrated on the substrate 110.

The first and second drain electrodes 175 a and 175 b are separated fromthe data lines 171 and disposed opposite the source electrodes 173 a and173 ba with respect to the first and second gate electrodes 124 a and124 b. Each of the drain electrodes 175 a and 175 b includes an endportion having an enlarged portion 177 a/177 b and a bar-shaped endportion, as illustrated in FIG. 3. The enlarged portion 177 a/177 b hasa large area which overlaps the storage electrode lines 131, and thebar-shaped end portion is disposed opposite the source electrodes 173 aand 173 b.

One gate electrode 124 a/124 b, one source electrode 173 a/173 b, andone drain electrode 175 a/175 b together with the semiconductor 154a/154 b constitute one thin film transistor (“TFT”), and channels of thethin film transistor are formed on the semiconductor 154 a/154 b betweenthe source electrode 173 a/173 b and the drain electrode 175 a/175 b.

The data lines 171 and the drain electrodes 175 a and 175 b arepreferably made of a molybdenum-based metal, chromium, a refractorymetal such as tantalum and titanium, or an alloy thereof, and may have amulti-layered structure which includes a refractory metal layer (notshown) and a low resistance conductive layer (not shown). Examples ofthe multilayered structure include a two-layered structure of a lowerchromium or molybdenum (alloy) layer and an upper aluminum (alloy) layerand a three-layered structure of a lower molybdenum (alloy) layer, anintermediate aluminum (alloy) layer, and an upper molybdenum (alloy)layer. However, the data lines 171 and the drain electrodes 175 a and175 b may be made of various metals and conductive materials notexplicitly listed herein.

The data lines 171 and the drain electrodes 175 a and 175 b may have atwo-layered structure which includes a refractory metal layer (notshown) and a low resistance conductive layer (not shown), or asingle-layered structure made of one of the various aforementionedmaterials. An example of the two-layered structure includes a lowerchromium or molybdenum (alloy) layer and an upper aluminum (alloy)layer. However, as mentioned above, the data lines 171 and the drainelectrodes 175 a and 175 b may be made of various metals and conductivematerials not explicitly listed herein.

The side surfaces of the data lines 171 and the drain electrodes 175 aand 175 b are slanted to form an angle ranging from about 30° to about80° with respect to the substrate surface.

The ohmic contact members 163 a, 163 b, 165 a and 165 b are interposedonly between the underlying semiconductors 154 a and 154 b and theoverlying data lines 171 and drain electrodes 175 a and 175 b, and havea function of reducing the contact resistance between the semiconductors154 and the overlying layers. The semiconductors 154 a and 154 b haveexposed portions which are not covered with the data lines 171 and thedrain electrodes 175 a and 175 b, for example, portions disposed betweenthe source electrodes 173 a and 173 b and the drain electrodes 175 a and175 b.

A passivation layer 180 is formed on the data lines 171, the drainelectrodes 175 a and 175 b, and the exposed portions of thesemiconductors 154. The passivation layer 180 includes a lower film 180p made of an inorganic insulating material such as silicon nitride andsilicon oxide, and an upper film 180 q made of an organic material. Theupper passivation film 180 q preferably has a dielectric constant ofless than 4.0, and it may have photosensitivity and an uneven surface.However, the passivation layer 180 may have a single-layered structuremade of an inorganic insulating material or an organic insulatingmaterial.

In the passivation layer 180, a plurality of contact holes 182, 185 aand 185 b which expose the end portions 179 of the data lines 171 andthe drain electrodes 175 a and 175 b, respectively, are formed. In thepassivation layer 180 and the gate insulating film 140, a plurality ofcontact holes 181 a and 181 b which expose the end portions 129 a and129 b of the gate lines 121 a and 121 b, respectively, are formed.

On the passivation layer 180, a plurality of first and second pixelelectrodes 191 a and 191 b and a plurality of contact assistance members81 a, 81 b and 82 are formed.

The first pixel electrode 191 a and the second pixel electrode 191 b arecurved along the unevenness of the passivation layer 180, and areseparated from each other, as illustrated in FIG. 4. The second pixelelectrode 191 b includes a transparent electrode 192 and a reflectiveelectrode 194 thereon. However, the transparent electrode 192 may beomitted in alternative exemplary embodiments.

The first pixel electrode 191 a and the transparent electrode 192 aremade of a transparent conductive material such as ITO and IZO, and thereflective electrode 194 is made of a reflective conductive materialsuch as aluminum, silver, chromium, or alloys thereof. However, thereflective electrode 194 may have a two-layered structure of an upperfilm (not shown) made of a low resistance reflective material such asaluminum, silver, or an alloy thereof, and a lower film (not shown) madeof a material having good contact characteristics to ITO and IZO, suchas a molybdenum-based metal, chromium, tantalum, or titanium.

The first pixel electrode 191 a is physically and electrically connectedthrough the contact hole 185 a to the first drain electrode 175 a toreceive data voltages from the first drain electrodes 175 a. The secondpixel electrode 191 b is physically and electrically connected throughthe contact hole 185 b to the second drain electrode 175 b to receivedata voltages from the second drain electrodes 175 b. The first/secondelectrode 191 a/191 b supplied with the data voltages generates anelectric field together with the common electrode 270 of the commonelectrode panel 200 supplied with a common voltage, so that alignment ofthe liquid crystal molecules of the liquid crystal layer 3 between thetwo pixel electrodes 191 a/191 b and the common electrode 270 can bedetermined. Polarization of light passing through the liquid crystallayer 3 changes according to the determined alignment of the liquidcrystal molecules. The first and second pixel electrodes 191 a and 191 band the common electrode 270 constitute liquid crystal capacitors tosustain the applied voltages even when the thin film transistors turnoff.

The transflective type of liquid crystal panel assembly 300 includingthe thin film transistor array panel 100, the common electrode panel200, and the liquid crystal layer 3 can be divided into a transmissiveregion and a reflective region which are defined by the first pixelelectrode 191 a and the second pixel electrode 191 b, respectively.

In the transmissive region, light incident from the front surface of theliquid crystal panel assembly 300, e.g., the common electrode panel 200,passes through the liquid crystal layer 3 to exit toward the rearsurface thereof, e.g., the thin film transistor array panel 100, therebyperforming display of an image. In the reflective region, light enteringfrom the front surface thereof enters into the liquid crystal layer 3,is reflected by the second pixel electrode 191 b, and passes through theliquid crystal layer 3 again to exit toward the front surface thereof,thereby performing display of an image. A curve of the second pixelelectrode 191 b surface improves the reflection efficiency of light.

The first and second pixel electrodes 191 a and 191 b and the enlargedportions 177 a and 177 b of the first and second drain electrodes 175 aand 175 b connected thereto constitute storage capacitors which overlapthe storage electrode lines 131 including the projections 137, andintensify the voltage sustaining capability of the liquid crystalcapacitors. Some parts of the storage electrode lines 131 overlap theenlarged portion 177 a of the first drain electrode 175 a, and the otherparts thereof overlap the enlarged portion 177 b of the second drainelectrode 175 b. As stated above, storage capacitors of two pixels PXaand PXb having the first pixel electrode 191 a or the second pixelelectrode 191 b are formed via one storage electrode line 131, therebyensuring transmittance.

The contact assistance members 81 a, 81 b and 82 are connected throughthe contact holes 181 a, 181 b and 182 to the end portions 129 a and 129b of the gate lines 121 a and 121 b and the end portions 179 of the datalines 171, respectively. The contact assistance members 81 a, 81 b and82 have a function of aiding adhesion of the end portions 129 a and 129b of the gate lines 121 a and 121 b and the end portions 179 of the datalines 171 to external apparatuses, and protecting these portions.

Now, the common electrode panel 200 will be described in more detailwith reference to FIG. 4.

A light-blocking member 220 is formed on a dielectric substrate 210 madeof transparent glass, plastic, or the like. The light-blocking member220 is often called a black matrix, and defines a plurality of openingsthat face the first pixel electrode 191 a and the second pixel electrode191 b. The light-blocking member 220 prevents light leakage between thefirst pixel electrode 191 a and the second pixel electrode 191 b.

A plurality of color filters 230 is formed on the substrate 210. Mostportions of each of the color filters 230 are disposed in the openingssurrounded by the light-blocking member 220. The color filters 230 mayextend along the first pixel electrode 191 a and the second pixelelectrode 191 b in a longitudinal direction to form stripes. Each of thecolor filters 230 can represent one of primary colors such as red, greenand blue, for example, but is not limited thereto.

An overcoat 250 is formed on the color filters 230 and thelight-blocking member 220. The overcoat 250 may be made of an (organic)insulating material, and protects the color filters 230, prevents thecolor filters 230 from being exposed, and provides a flat surface.However, the overcoat 250 may be omitted in alternative exemplaryembodiments.

The common electrode 270 is formed on the cover film 250. The commonelectrode 270 is preferably made of a transparent conductive materialsuch as ITO and IZO.

An alignment film (not shown) for aligning the liquid crystal layer 3 iscoated on inner or outer surfaces of the panels 100 and 200. Polarizers(not shown) are provided on inner or outer surfaces of the panels 100and 200.

The liquid crystal layer 3 may be vertically or horizontally aligned.

The liquid crystal panel assembly 300 further includes a plurality ofelastic spacers (not shown) for supporting the thin film transistorarray panel 100 and the common electrode panel 200 to form a suitablegap therebetween.

The liquid crystal panel assembly 300 may further include a sealant (notshown) for bonding the thin film transistor array panel 100 and thecommon electrode panel 200 together. The sealant is disposed at an edgeof the common electrode panel 200.

Referring to FIG. 1 again, the gray voltage generator 800 generates twograyscale voltage sets (reference grayscale sets) corresponding to atransmittance of the pixels PX. One of the two grayscale sets has apositive value with respect to the common voltage Vcom, and the othergrayscale set has a negative value with respect to the common voltageVcom.

The gate driver 400 includes first and second gate driving circuits 400Land 400R, and the gate driving circuits 400L and 400R are connected tothe gate lines G₁-G_(2n) of the liquid crystal panel assembly 300 toapply gate signals formed in a combination of a gate-on voltage Von anda gate-off voltage Voff to the gate lines G₁-G_(2n).

The first gate driving circuit 400L is disposed at a left side of theliquid crystal panel assembly 300 and applies gate signals to first gatelines G_(2j-1)(j=1, 2, . . . n) (GLa of FIG. 2). The second gate drivingcircuit 400R is disposed at a right side of the liquid crystal panelassembly 300 and applies gate signals to second gate lines G_(2j) (GLbof FIG. 2). The first gate driving circuit 400L and the second gatedriving circuit 400R apply a gate-on voltage Von, starting from the gateline disposed on the uppermost side of the liquid crystal panel assembly300, and alternately output the gate-on voltage Von.

The data driver 500 is connected to the data lines D₁-D_(m) of theliquid crystal display panel assembly 300 to select a gray voltage fromthe gray voltage generator 800 and apply it to the data lines D₁-D_(m)as a data signal.

The backlight unit 900 is, as shown in FIG. 4, disposed to be close tothe common electrode panel 200 rather than the thin film transistorarray panel 100 of the liquid crystal panel assembly 300, to irradiatelight toward the thin film transistor array panel 100 from the commonelectrode panel 200. The backlight unit 900 may include a light source910 for generating light, a light conducting plate 920 for guiding anddiffusing light from the light source 910 toward the liquid crystalpanel assembly 300, and an optical sheet 930. The light conducting plate920 may have a shape similar to that of the common electrode panel 200,and the optical sheet 930 may be disposed between the light conductiveplate 920 and the common electrode panel 200. A fluorescent lamp orlight emitting diode LED may be used as the light source 910, and may bearranged at a side of the light conductive plate 920.

Referring again to FIG. 1, the signal controller 600 externally receivesinput image signals R, G and B for images on the front and rear surfacesof the liquid crystal panel assembly 300 from the outside, processesthem to generate output image signals DAT, and controls the gate driver400, the data driver 500, and the like.

Such a signal controller 600 will be described in more detail later.

Each of the drivers 400, 500, 600 and 800 may be directly mounted in aform of at least one integrated circuit chip on the liquid crystaldisplay panel assembly 300, may be attached in a form of a tape carrierpackage (“TCP”) on a flexible printed circuit (“FPC”) film (not shown)in the liquid crystal display panel assembly 300, or may be mounted on aseparate printed circuit board (“PCB”) (not shown). Alternatively, thesedrivers 400, 500, 600 and 800 together with the signal lines G₁-G_(2n)and D₁-D_(m) and the thin film transistor switching elements Qa and Qbmay be directly mounted on the liquid crystal display panel assembly300. Further, the drivers 400, 500, 600 and 800 may be integrated as asingle chip, in which case, at least one of them or at least one circuitdevice constituting them may be located outside of the single chip.

Now, the operation of the liquid crystal display device will bedescribed in more detail.

The signal controller 600 is supplied with input image signals R, G andB and input control signals controlling the display thereof from anexternal graphics controller (not shown). The input image signals R, Gand B contain luminance information of each pixel PXa/Pxb, and theluminance has a predetermined number, for example, 1024 (=2¹⁰), 256(=2⁸) or 64 (=2⁶) gray scales. The input control signals include, forexample, a vertical synchronization signal Vsync, a horizontalsynchronization signal Hsync, a main clock signal MCLK and a data enablesignal DE.

In response to the input image signals R, G and B and the input controlsignals, the signal controller 600 processes the input image signals R,G and B suitably for operation of the liquid crystal panel assembly 300and generates output image signals DAT, gate control signals CONT1 anddata control signals CONT2, and then outputs the gate control signalsCONT1 to the gate driver 400 and the data control signals CONT2 and theoutput image signals DAT to the data driver 500.

The gate control signals CONT1 include a scanning start signal STV forinstructing the start of scanning and at least one clock signal forcontrolling an output time of the gate-on voltage Von. The gate controlsignals CONT1 may further include an output enable signal OE fordefining a duration of the gate-on voltage Von.

The data control signals CONT2 include a horizontal synchronizing startsignal STH for informing of a beginning of transmission of digitaloutput image signals DAT for a row of pixels PXa and PXb, a load signalLOAD for instructing to apply analog data voltages to the data linesD₁-D_(m), and a data clock signal HCLK. The data control signals CONT2may further include a reverse signal RVS for reversing a polarity of theanalog data voltages with respect to the common voltage Vcom(hereinafter, a polarity of the analog data voltages will be abbreviatedas a polarity of the data voltages).

Responsive to the data control signals CONT2 from the signal controller600, the data driver 500 receives digital image signals DAT for a row ofpixels PXa and PXb from the signal controller 600, converts the digitaloutput image signals DAT into analog data voltages by selectinggrayscale voltages corresponding to the output image signals DAT, andthen applies the analog data voltages to corresponding data linesD₁-D_(m).

The gate driver 400 applies the gate-on voltage Von to the gate linesG₁-G_(2n) in response to the gate control signals CONT1 from the signalcontroller 600, thereby turning on switching elements Qa/Qb connected tothe gate lines G₁-G_(2n). The data voltages applied to the data linesD₁-D_(m) are applied to corresponding pixels PXa/PXb through turned-onswitching elements Qa/Qb.

The first gate driving circuit 400L and the second gate driving circuit400R alternately apply the gate-on voltage Von, and accordingly thefirst pixel PXa and the second pixel PXb are alternately supplied withthe data voltages.

The difference between the data voltage applied to the pixels PXa andPXb and the common voltage Vcom becomes a charged voltage of the liquidcrystal capacitors Clca and Clcb, that is, a pixel voltage. Alignment ofthe liquid crystal molecules varies according to the intensity of thepixel voltage. Polarization of light passing through the liquid crystallayer 3 changes according to the alignment of the liquid crystalmolecules. The change in the polarization results in a change intransmittance of the light due to the polarizers attached to the liquidcrystal panel assembly 300. Thus, the pixels PXa and PXb display aluminance represented by the grayscales of the output image signals DAT.

As explained above, the first pixel PXa displays images on the rearsurface of the liquid crystal panel assembly 300, and the second pixelPXb displays images on the front surface of the liquid crystal panelassembly 300.

By repeating the above-mentioned procedure every 2 horizontal periods(in which 1 horizontal period is equal to one period of the horizontalsynchronization signal Hsync and the data enable signal DE), all gatelines G₁-G_(2n) are sequentially supplied with the gate-on voltage Von,thereby applying the data voltages to all pixels PXa and PXb to displayimages for the front surface of one frame and images for the rearsurface of one frame.

Subsequently, two different kinds of pixels PXa and PXb can displayimages with a different constant phase on the front and rear surfaces ofthe liquid crystal panel assembly. The sizes of the images on the frontand rear surfaces may not be identical to each other, and may be variedaccording to design.

When one frame ends, the next frame starts, and a state of the reversesignal RVS applied to the data driver 500 is controlled so that thepolarity of the data signal applied to each of the pixels PXa and PXb isopposite to the polarity in the previous frame (frame inversion). Atthis time, even in one frame, according to the characteristics of thereverse signals RVS, the polarities of the data voltages flowing throughthe data lines may be inverted (row inversion and dot inversion), andthe polarities of the data voltages applied to one pixel row may bedifferent from each other (column inversion and dot inversion).

Now, the signal controller 600 according to the exemplary embodiment ofthe present invention will be described in more detail with reference toFIGS. 6 to 8.

FIG. 6 is a block diagram of a signal controller according to anexemplary embodiment of the present invention.

Referring to FIG. 6, the signal controller 600 according to an exemplaryembodiment of the present invention includes a first receiver 610, asecond receiver 620, a signal arrangement unit 630, and a timing controlunit 650, and the signal controller 600 generates output image signalsDAT based on input image signals R, G and B.

The first receiver 610 and the second receiver 620 are interfacesbetween an external system and a liquid crystal display device. Thefirst/second receivers 610/620 receive first/second input image signalsDin1/Din2 and first/second control signals CT1/CT2. The first inputimage signal Din1 is an image signal to be displayed on one of the frontand rear surfaces of the liquid crystal panel assembly 300, and thesecond input image signal Din2 is an image signal to be displayed on theother surface thereof. The input image signals R, G and B to bedisplayed on the front surface are related to the second pixels PXb,e.g., the second pixel electrode 191 b in FIGS. 3 and 5, and the inputimage signals R, G and B to be displayed on the rear surface are relatedto the first pixels PXa, e.g., the first pixel electrode 191 b in FIGS.3 to 5.

The first receiver 610 is, for example, a central processing unit(“CPU”) interface, and includes a receiving terminal 611 and a framememory 615. The receiving terminal 611 receives the first input imagesignal Din1, and processes the received first input image signal Din1 inresponse to the first input control signal CT1 to output the same to theframe memory 615. The receiving terminal 611 may include a plurality ofregisters (not shown) for processing the first input image signal Din1in response to the first input control signal CT1. Such receivingterminal 611 can be controlled in response to the first input imagesignal CT1 according to a user's intention. The frame memory 615 storesthe processed first input image signal Din1.

The second receiver 620 is, for example, an RGB interface. The secondreceiver 620 does not include a separate frame memory, and it receivesthe second input image signal Din2 and the second input control signalCT2. The second control signal CT2 is a signal representing timeinformation of the second input image signal Din2, for example, avertical synchronization signal Vsync, a horizontal synchronizationsignal Hsync, and a data enable signal DE.

The first receiver 610 and the second receiver 620 may receive the inputimage signals Din1 and Din2 in an alternating fashion. For example, thefirst receiver 610 firstly receives the first input image signal Din1 tostore it in the frame memory 615, and thereafter the second receiver 620starts to receive the second input image signal Din2.

Alternatively, the first receiver 610 and the second receiver 620 maysimultaneously receive the input image signals Din1 and Din2. In thiscase, the first input image signal Din1 forming a pair with the secondinput image signal Din2, being received by the second receiver 620, mayenter into the first receiver 610 in advance and be stored in the framememory 615. The first input image signal Din1, currently being inputtedinto the first receiver 610, may form a pair with the second input imagesignal Din2 of the next frame.

The signal arrangement unit 630 includes first, second and third linememories 631, 633 and 635, and determines whether the input imagesignals Din1 and Din2 of the receivers 610 and 620, respectively, aresignals to be displayed on the front surface of the liquid crystal panelassembly 300 or on the rear surface thereof. The signal arrangement unit630 sequentially arranges the signals according to the result ofdetermination to generate output image signals DAT, and outputs them toan output terminal OUT.

The first line memory 631 is connected to the frame memory 615 of thefirst receiver 610, and receives the first input image signal Din1 forone pixel row from the frame memory 614 and stores it. The second linememory 633 is connected to the second receiver 620, and receives thesecond input image signal Din2 from the second receiver 620 and storesit in units of one pixel row.

The third line memory 635 is connected between the first and second linememories 631 and 633 and the output terminal OUT. The third line memory635 alternately reads the first and second input image signals Din1 andDin2 stored in the first line memory 631 and the second line memory 633,respectively, and alternately outputs the read input image signals Din1and Din2 in the order of reading. The image signals outputted by thethird line memory 635 become output image signals DAT.

The issue of which of the two line memories 631 and 633 is to beaccessed first by the third memory 635 in order to extract image signalsR, G and B is determined according to which is for use in the frontdisplay and which is for use in the rear display between the first inputimage signal Din1 and the second input image signal Din2. For example,if a pixel row of the first pixels PXa used for rear display receives adata voltage first, and a pixel row of the second pixels PXb used forfront display receives a data voltage later, the third line memory 635first accesses the memory storing the image signal for front displaybetween the first and second memories 631 and 633.

In the meantime, since the first line memory 631 and the second linememory 633 should be read alternately, the reading frequency may betwice that of the writing frequency.

If the first receiver 610 and the second receiver 620 simultaneouslyreceive the input image signals Din1 and Din2, the frame frequency ofthe output image signals DAT is twice the frame frequency of the inputimage signals Din1 and Din2. That is, whenever the first or second inputimage signal Din1 or Din2 for one pixel is inputted, a data voltage isapplied to one row of the first pixels and one row of the second pixels.

In the meantime, the signal control unit 650 is for synchronization ofthe frame memory 615 and the line memories 631, 633 and 635. The timecontrol unit 650 receives a second control signal CT2, which is a timecontrol signal, from the second receiver 620, and generates a controlsignal for controlling the input and output of the memories 615, 631,633 and 635.

Specifically, the time control unit 650 provides the frame memory 615with a control signal for outputting the first input image signal Din1of one pixel row to the first line memory 631 by synchronization withthe second receiver 620 when the second receiver 620 outputs the secondinput image signal Din2 of one pixel row to the second line memory 633.The time control unit 650 also provides a control signal to the firstand second memories 631 and 633 for setting the output order of thefirst line memory 631 and second line memory 633, respectively. Further,the time control unit 650 provides a control signal to the third linememory 635 for controlling the third line memory 635.

As described above, by using two interfaces of different types, it ispossible to display images on both opposing surfaces of the liquidcrystal panel assembly 300 with only one frame memory 615.

In some cases, identical images may be displayed on both opposingsurfaces of the liquid crystal panel assembly 300, and FIGS. 7 and 8show an example thereof. Here, the displaying of identical images meansthat an image viewed from the front surface of the liquid crystal panelassembly 300 and an image viewed from the rear surface thereof areidentical to each other.

FIG. 7 is a block diagram of a signal controller according to anotherexemplary embodiment of the present invention.

An external system is able to transmit input image signals in adifferent interface method depending on the characteristics of images.For example, if an image to be displayed is a still image, the imagesignal is transmitted in a CPU interface method. On the contrary, if animage to be displayed is a moving image, the image signal is transmittedin an RGB interface method. The signal controller 600 as shown in FIG. 7can be adapted to such a case.

Referring to FIG. 7, the signal controller 600 according to anotherexemplary embodiment of the present invention includes a selection unit640, a first receiver 610, a second receiver 620, a signal arrangementunit 660, and a timing control unit 650, and has two input terminals,e.g., first and second input terminals IN1 and IN2.

The first and second receivers 610, 620 and the time control unit 650are identical to those of the signal controller 600 of FIG. 6.

The selection unit 640 includes a first switch SW1 connected between thefirst input terminal IN1 and the first receiver 610 and a second switchSW2 connected between the second input terminal IN2 and the secondreceiver 620.

The first and second switches SW1 and SW2 are selectively operateddepending on the interface method of input image signals R, G and B, andtransmit the input image signals R, G and B to the correspondingreceivers 610 and 620. The operation of the first and second switchesSW1 and SW2 can be externally controlled through control signals CT3 andCT4 inputted together with the input image signals R, G and B.

In this manner, only one of the two receivers 610 and 620 is operated,and the other one is not operated, thereby reducing power consumption.

The signal arrangement unit 660 includes first, second and third linememories 661, 663 and 665, and a plurality of switches S1-S5 connectedthereto.

The first line memory 661 is connected to a frame memory 615 of thefirst receiver 610, the second line memory 663 is connected to thesecond receiver 620, and the third memory 665 is connected to an outputterminal OUT.

The switch S1 is connected between the first line memory 661 and theoutput terminal OUT, the switch S2 is connected between the second linememory 663 and the output terminal OUT, the switch S3 is connectedbetween the first line memory 661 and the third line memory 665, theswitch S4 is connected between the second line memory 663 and the thirdline memory 665, and the switch S5 is connected between the third linememory 665 and the output OUT.

If the first receiver 610 operates, the switches S1, S3 and S5 areturned on, and if the second receiver 620 operates, the switches S2, S4and S5 are turned on. The switches S1-S4 and the switch S5 operate in analternating fashion.

An example of the operation of the first receiver 610 will be described.

First, when the switches S1 and S3 are turned on, the stored input imagesignals R, G and B of the first line memory are output to the outputterminal OUT through the switch S1, and transmitted to the third linememory 665 through the switch S3 and stored therein.

When the output of the first line memory 661 is finished, the switchesS1 and S3 are turned off to cut off the output of the first line memory661, and the switch S5 is turned on to output the input image signals R,G and B stored in the third line memory 665 to the output terminal OUT.

The switches S2, S4 and S5 operate in the same manner as described abovewhen the second receiver 620 operates.

As described above, in a case where the liquid crystal display devicehaving two interfaces of different types displays identical images onboth opposing surfaces, it is possible to generate output image signalsDAT for displaying identical images on both opposing surfaces of theliquid crystal panel assembly 300 while reducing power consumption bystopping one of the interfaces.

Meanwhile, when the signal controller 600 of FIG. 7 displays differentimages on both surfaces of the liquid crystal panel assembly 300, thefirst and second switches SW1 and SW2 of the selection unit 640 aresimultaneously turned on to simultaneously operate the first and secondreceivers 610 and 620, and the switches S3, S4 and S5 are turned on andthe switches S1 and S2 are turned off. In this manner, the signalarrangement unit 660 of FIG. 7 can operate in the same manner as thesignal controller 600 of FIG. 6.

Next, the signal controller 600 according to still another exemplaryembodiment will be described with reference to FIG. 8.

FIG. 8 is a block diagram of a signal processor according to stillanother exemplary embodiment of the present invention.

The signal controller as shown in FIG. 8 can be adapted to a case wherethe interface method of an external system is fixed to any one method.

Referring to FIG. 8, the signal controller 600 according to the presentexemplary embodiment includes a selection unit 640, a first receiver610, a second receiver 620 and a time control unit 650 having one inputterminal IN.

The first and second receivers 610 and 620 and the time control unit 650are identical to those of the signal controller 600 of FIG. 6.

The selection unit 640 includes one switch SW3 for connecting one of thefirst and second receivers 610 and 620 to the input terminal IN.

The switch SW3 of the selection unit 640 connects the input terminal INand the first receiver 610 or connects the input terminal IN and thesecond receiver 620 depending on the interface method of input imagesignals R, G and B to transmit the input image signals R, G and B to thereceivers 610 and 620. The operation of the switch SW3 can be externallycontrolled through a control signal CT inputted together with the inputimage signals R, G and B.

The signal arrangement unit 670 includes first and second line memories671 and 675 and a delay buffer 673. The first line memory 671 isconnected between the first receiver 610 and an output terminal OUT. Thesecond line memory 620 is connected between the second receiver 620 andthe output terminal OUT. The delay buffer 673 is connected to the firstand second receivers 610 and 620 and the memories 671 and 675, anddelays an input signal by a predetermined time and sends it.

In the signal controller 600 as shown in FIG. 8, only one of the tworeceivers 610 and 620 is operated, and the other one is not operated,thereby reducing power consumption. For instance, it is assumed thatonly the first receiver 610 operates. In this case, an image signaloutputted from the first receiver 610 is stored in the first line memory671, and at the same time is stored in the delay buffer 673. The imagesignal stored in the first line memory 671 is outputted directly, andthe image signal stored in the delay buffer 673 is delayed by apredetermined time and stored in the second line memory 675, and thenoutputted when the output of the first line memory 671 is finished. Theduration of delay in the delay buffer 673 is equal to the time duringwhich the first line memory 671 outputs an image signal.

In the meantime, in order to display images with constant phases on bothfront and rear surfaces of one liquid crystal panel assembly 300, whenviewed from one surface, the image displayed on the opposite sidesurface is a reverse image whose left and right or top and bottom arereversed. Therefore, for example, in a case where the input imagesignals R, G and B are sequentially arranged with respect to the imageon the front surface of the liquid crystal panel assembly 300, in orderto display image with constant phases on the rear surface, it isnecessary to reverse the order of image signals to be displayed on therear surface for outputting them.

The signal controller 600 as shown in FIG. 6 receives an input imagesignal for front display and an input image signal for rear displayseparately. Thus, when an external apparatus sends the input imagesignal for rear display to the signal controller 600, it can be sent inorder so as to be directly outputted.

However, in FIGS. 7 and 8, the signal controller 600 receives one imagesignal and outputs it twice. Thus, when the image signal is outputtedfor use in the rear display, the order thereof needs to be changed. Forthis, any one of the line memories 661, 663, 665, 671 and 675 iswritable and readable in reverse order. For example, in FIG. 8, thefirst line memory 671 is writable in order, and the second line memory675 is writable in reverse order.

As seen from the above, according to the present invention, by using twodifferent interfaces in the liquid crystal display device, memories canbe reduced by driving transmissive pixels and reflective pixelsindependently, and different normal images can be displayed on bothsurfaces of the display panel. When the same image is displayed on bothsurfaces, only one interface is selectively driven to thereby reducepower consumption.

While the present invention has been described in connection with whatis presently considered to be practical exemplary embodiments, it is tobe understood that the present invention is not limited to the disclosedexemplary embodiments, but, on the contrary, is intended to covervarious modifications and equivalent arrangements included within thespirit and scope of the appended claims.

1. A dual display device, comprising: a display panel having a firstsurface and an opposing second surface, and including a plurality offirst pixels displaying an image on the first surface and a plurality ofsecond pixels displaying an image on the second surface; a gate driversupplying gate signals to the first and second pixels; a signalcontroller including first and second receivers receiving input imagesignals, and generating first and second output image signals based onthe input image signals; and a data driver analog-converting the firstand second output image signals to generate first and second datavoltages, respectively, and supplying the first and second data voltagesto the first and second pixels, respectively.
 2. The dual display deviceof claim 1, wherein the first pixels and the second pixels are arrangedin an alternating fashion.
 3. The dual display device of claim 2,wherein the display panel comprises data lines connected to the firstand second pixels, and the data driver applies the first data voltageand the second data voltage to the data lines in an alternating fashion.4. The dual display device of claim 3, wherein the first pixel comprisesa transmissive pixel electrode, and the second pixel includes areflective pixel electrode.
 5. The dual display device of claim 4,further comprising a backlight unit irradiating light toward the displaypanel, wherein the transmissive pixel electrode transmits the light fromthe backlight unit toward the first surface of the display panel, andthe reflective pixel electrode reflects the light from the backlightunit toward the second surface thereof.
 6. The dual display device ofclaim 1, wherein the signal controller further comprises a signalarrangement unit generating the first output image signal and the secondoutput image signal based on the input image signals received from atleast one of the first and second receivers, and outputting the firstoutput image signal and the second output image signal to the datadriver in an alternating fashion.
 7. The dual display device of claim 6,wherein the first receiver comprises a first memory unit which storesthe image signals.
 8. The dual display device of claim 7, wherein thefirst receiver is controlled by an external control signal.
 9. The dualdisplay device of claim 7, wherein the input image signals comprises afirst input image signal to be displayed on the first surface and asecond input image signal to be displayed on the second surface, thefirst receiver receives the first input image signal to store the samein the first memory unit, the second receiver receives the second inputimage signal to output the same, and the signal arrangement unitgenerates the first output image signal from the first input imagesignal and the second output image signal from the second input imagesignal.
 10. The dual display device of claim 9, wherein the signalarrangement unit comprises: a second memory unit receiving the firstinput image signal from the first memory unit to store the same therein;a third memory unit receiving the second input image signal from thesecond receiver to store the same therein; and a fourth memory unitreceiving the first input image signal and the second input image signalfrom the second memory unit and the third memory unit in an alternatingfashion to store the same therein.
 11. The dual display device of claim10, wherein an image of the first pixels and an image of the secondpixels are different from each other.
 12. The dual display device ofclaim 7, wherein an image viewed from the first surface of the displaypanel and an image viewed from the second surface thereof are identicalto each other.
 13. The dual display device of claim 12, wherein thesignal controller generates the first output image signal and the secondoutput image signal based on the input image signals received from atleast one of the first and second receivers.
 14. The dual display deviceof claim 13, wherein the signal controller further comprises a firstswitching unit selecting one of the first and second receivers andtransmitting the input image signals thereto.
 15. The dual displaydevice of claim 14, wherein the first switching unit comprises: a firstswitch monitoring a connection between the first receiver and the inputimage signals; and a second switch monitoring a connection between thesecond receiver and the input image signals and operating opposite tothe first switch.
 16. The dual display device of claim 14, wherein thefirst switching unit comprises a switch connected to the input imagesignals and selectively connected to one of the first and secondreceivers.
 17. The dual display device of claim 14, wherein the signalarrangement unit comprises a delay unit which delays the input imagesignals.
 18. The dual display device of claim 17, wherein the signalarrangement unit further comprises: a second memory unit connected tothe first receiver; and a third memory unit connected to the secondreceiver, and the signal arrangement unit has an output terminal. 19.The dual display device of claim 18, wherein the delay unit receives theinput image signals from one of the second and third memory units. 20.The dual display device of claim 19, wherein the signal arrangement unitcomprises a second switching unit monitoring the connection among thesecond memory unit, the third memory unit, the delay unit and the outputterminal.
 21. The dual display device of claim 20, wherein the secondswitching unit comprises: a first switch monitoring a connection betweenthe second memory unit or the third memory unit and the output terminal;a second switch monitoring a connection between the second memory unitor the third memory unit and the delay unit; and a third switchmonitoring a connection between the delay unit and the output terminal.22. The dual display device of claim 21, wherein a conduction time ofthe first switching unit and the second switching unit are differentfrom a conduction time of the third switching unit.
 23. The dual displaydevice of claim 18, wherein the delay unit receives the input imagesignals from one of the first and second receivers and outputs the inputimage signals to one of the second and third memory units.
 24. The dualdisplay device of claim 16, wherein the signal arrangement unit outputsthe first output image signal and the second output image signal in areverse order.